MCF5202 ColdFireMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 ColdFire Integrated Microprocessor User's Manual describes the programming, capabilities, and operation of the MCF5202 device. Refer to the MCF5200 ColdFire Family Programmer's Reference Manual for information on the ColdFire Family of microprocessors. TRADEMARKS All trademarks reside with their respective owners.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUAL viiMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 Block Diagram.......................................................................................... 2-1 2-2 Data Bit Assignments to External Port Sizes ........................................................... 2-5 Section 3 ColdFire Core 3-1 3-2 3-3 3-4 3-5 ColdFire Processor Core Pipeline ........................................................................... 3-1 User Programming Model ........................................................................................ 3-3 Supervisor Programming Model .............................................................................. 3-4 Status Register ........................................................................................................ 3-5 Exception Stack Frame Form ................................................................................... 3-7 Section 4 Cache 4-1 4-2 4-3 4-4 4-5 4-6 MCF5202 Unified Cache ......................................................................................... 4-1 Cache Organization and Line Format ...................................................................... 4-2 Caching Operation ................................................................................................... 4-3 Cache Control Register ........................................................................................... 4-5 Access Control Register Format .............................................................................. 4-7 Cache Line State Diagrams ................................................................................... 4-16 Section 5 Bus Operations 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 Signal Relationships to CLK .................................................................................... 5-1 Simple Transfer Followed by Transfer Containing Bus Error .................................. 5-2 Dynamically Sized Burst-Inhibited Read Access ..................................................... 5-3 Dynamically Sized Burst-Inhibited Write Access ..................................................... 5-3 Dynamically Sized Burst Read ................................................................................ 5-4 Dynamically Sized Burst Write.................................................................................. 5-4 Interrupt-Acknowledge Operation ............................................................................. 5-5 Bus Arbitration Operation ......................................................................................... 5-6 Reset Operation........................................................................................................ 5-7MCF5202 USER'S MANUALMCF5202 Mechanical Specs.................................................................................. 10-1 10-2 MCF5202 Pinout..................................................................................................... 10-2MCF5202 USER'S MANUALMCF5202 Data Formats............................................................................. 1-7 ColdFire Effective Addressing Modes...................................................................... 1-8 Specific Effective Addressing Modes........................................................................ 1-8 MOVE Specific Effective Addressing Modes ............................................................ 1-8 Notational Conventions............................................................................................. 1-9 Supervisor-Mode Instruction Summary .................................................................. 1-12 User Mode Instruction Summary ............................................................................ 1-12 Section 2 Signal Description 2-1 2-2 2-3 2-4 2-5 2-6 2-7 MCF5202 Signal Index ............................................................................................. 2-2 Bus Cycle Size Encodings ....................................................................................... 2-3 Bus Cycle Transfer Type Encoding .......................................................................... 2-4 Access/Mode Encodings .......................................................................................... 2-4 External Data Acknowledge Encodings.................................................................... 2-5 MCF5202 Processor PST Definition......................................................................... 2-7 MTMOD Definition .................................................................................................... 2-8 Section 3 ColdFire Core 3-1 Exception Vector Assignments ................................................................................ 3-7 3-2 Format Field Encodings ........................................................................................... 3-8 3-3 Fault Status Encodings ............................................................................................ 3-8 3-4 Misaligned Operand References ............................................................................ 3-12 3-5 Move Byte and Word Execution Times................................................................... 3-13 3-6 Move Long Execution Times .................................................................................. 3-13 3-7 One Operand Instruction Execution Times............................................................. 3-14 3-8 Two Operand Instruction Execution Times............................................................. 3-15 3-9 Miscellaneous Instruction Execution Times............................................................ 3-16 3-10 General Branch Instruction Execution Times ......................................................... 3-17 3-11 BRA, Bcc Instruction Execution Times ................................................................... 3-17 Section 4 Cache 4-1 Cache Line State Transitions ................................................................................. 4-16MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 processor is a ColdFire Family member that has been optimized for costeffective performance in deeply embedded applications. The MCF5202 processor can operate on a 32-, 16-, or 8-bit external data bus.MCF5202 USER'S MANUALMCF5202 processor include the following: * Best-in-Class Code Density -- Requires less memory than fixed length RISC equivalents -- Allows use of slower memory for a given performance level than fixed-length RISCs -- Improves cache effectiveness * Dynamic Bus Sizing -- 32-, 16-, and 8-bit bus support on the MCF5202 processor * 2 kbyte On-Chip Unified Cache -- High performance 4-way set associative, non-blocking cache implementation * Simple Instruction Set Architecture -- Optimized for high-level language constructs -- Requires minimal silicon area to implement processor core -- 16 user-visible 32-bit wide general-purpose registers -- Supervisor / user modes for system protection -- Vector base register to relocate exception-vector table * Debug Module Including Background Debug and Real Time Debug Support * Low Interrupt Latency * Full Static Design Allows Operation Down to DC for Minimizing Power Consumption * Three-State Pin * JTAG IEEE 1149.1 Test Interface * Single Clock InputMCF5202 USER'S MANUALMCF5202 processor. The MCF5202 device consists of a pipelined instruction execution unit, a two-kbyte unified cache, a debug module, and an external bus controller that supports the IEEE 1149.1 JTAG interface. The instruction execution unit is comprised of two separate pipelines that are decoupled by an instruction buffer. The instruction fetch pipeline (IFP) is responsible for instruction address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions waiting for execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first decodes instructions and selects operands; the second calculates operand effective addresses, if needed, and performs instruction execution.MCF5202 processor uses a unified data/instruction cache to improve overall system performance. The primary improvement is because of the availability of the most recently used instructions and data in a memory that can be accessed by the processor core in a single cycle. A second improvement is the increased external bus bandwidth available for alternate bus masters in the system. The nonblocking cache is organized as 4-way set associative and is physically mapped, thereby reducing software support for multitasking operating systems. The bus controller performs bus transfers on the external bus. The MCF5202 bus controller supports a high-speed, multiplexed, synchronous, external bus interface. This interface in turn supports burst accesses for both reads and writes to provide high data transfer rates to and from the internal cache. The bus controller also supports the industry-standard IEEE 1149.1 JTAG interface.MCF5202 USER'S MANUALMCF5202 processor cannot complete the transition to normal processing nor can it save the internal machine state. The processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. When the processor executes a STOP instruction, it is in a special type of normal processing state, e.g., one without bus cycles. The processor stops but it does not halt. The processor can also halt in a restart mode because of Background Debug Mode events.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 device is executing, and the lower byte of the SR, which is accessible as the Condition Code Register (CCR). The CCR contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The supervisor programming model includes the upper byte of the SR, which contains operation control information. The Vector Base Register (VBR) contains the upper 12 bits of the base address of the exception vector table, which is used in exception processing. TheMCF5202 USER'S MANUALMCF5202 processor. There are two access control registers (ACR1, ACR0) that allow portions of the address space to be mapped as noncacheable. See Sections 4.3 and 4.4 for more details on these registers.MCF5202 data formats. Table 1-1. ColdFire MCF5202 Data FormatsMCF5202 processor supports seven addressing modes. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated embedded applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required to support position-independent software. Besides these addressing modes, the MCF5202 processor provides index scaling features. An instruction's addressing mode can specify the value of an operand or a register containing the operand. It can also specify how to derive the effective address of an operand in memory. Each addressing mode has an assembler syntax. Some instructions imply the addressing mode for an operand. These instructions include the appropriate fields for operands that use only one addressing mode. Table 1-2 lists a summary of the effective addressing modes of ColdFire processors.MCF5202 USER'S MANUAL Dn An (An) (An)+ DESTINATION All All All AllMCF5202 USER'S MANUAL -(An) DESTINATION All Dn An (An) (An)+ -(An) (d16,An) Dn An (An) (An)+ -(An) Dn An (An) (An)+ -(An) Dn An (An) (An)+ -(An)MCF5202 USER'S MANUAL y,x + - x / ~ & | ~ << >> sign-extended If then else Logical Condition (example: NE for not equal) REGISTER OPERANDS Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively Any Data Register n (example: D5 is data register 5) Source and destination data registers, respectively Any Address or Data Register Any source and destination registers, respectively Any second destination register Any Control Register (example VBR is the vector base register) REGISTER/PORT NAMES Debug Data Port Condition Code Register (lower byte of status register) Program Counter Processor Status Port Status Register MISCELLANEOUS OPERANDS Immediate data following the instruction word(s) Effective Address Source and Destination Effective Addresses, respectively Assembly Program Label List of registers (example: D3-D0) Operand data size: Byte (B), Word (W), Longword (L) OPERATIONS Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator Arithmetic multiplication Arithmetic division Invert; operand is logically complemented Logical AND Logical OR Logical exclusive OR Shift left (example: D0 << 3 is shift D0 left 3 bits) Shift right (example: D0 >> 3 is shift D0 right 3 bits) Source operand is moved to destination operand Two operands are exchanged All bits of the upper portion are made equal to the high-order bit of the lower portion Test the condition. If true, the operations after `then' are performed. If the condition is false and the optional `else' clause is present, the operations after `else' are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.MCF5202 USER'S MANUALMCF5202 USER'S MANUALx y,Dx y,Ax #,Dx #,x Dy,Dx Dy,x y,Dx #,Dx Dx,Dy #,Dx Dx,Dy ,Dx Dy,x #,x Dy,x #,x Dy,x #,x Dy,x #,x x #,Dx y,Dx y,Ax (An) Dy,x #,Dx Dx Dx Dx none y,Ax Ax,# Dx,Dy #,Dx Dx,Dy #,Dx OPERAND SIZE 32 32 32 32 32 32 32 32 32 32 32 32 32 8,16 8,32 8,32 8,32 8,32 8,16 8,32 8,32 8,16 8,32 8,32 8,16,32 32 32 32 32 32 32 8 16 16 32 8 32 none none 32 32 16 32 32 32 32 OPERATION Source + Destination Destination Source + Destination Destination Immediate Data + Destination Destination Immediate Data + Destination Destination Source + Destination + X Destination Source & Destination Destination Immediate Data & Destination Destination X/C (Dy << Dx) 0 X/C (Dy << #) 0 MSB (Dy >> Dx) X/C MSB (Dy >> #) X/C If Condition True, Then PC + dn PC ~( of Destination) Z, Bit of Destination ~( of Destination) Z; 0 Bit of Destination PC + dn PC ~( of Destination) Z; 1 Bit of Destination SP - 4 SP; next sequential PC (SP); PC + dn PC ~( of Destination) Z 0 Destination Destination - Immediate Data Destination - Source Destination - Source Push and Invalidate Cache Line Source ~ Destination Destination Immediate Data ~ Destination Destination Sign-Extended Destination Destination Sign-Extended Destination Destination Enter Halted State Address of PC SP- 4 SP; next sequential PC (SP); PC Ax SP - 4 SP; Ax (SP); SP Ax; SP + d16 SP X/C (Dy << Dx) 0 X/C (Dx << #) 0 0 (Dy >> Dx) X/C 0 (Dx >> #) X/CMCF5202 USER'S MANUALy,x Dx Dx Dy,CCR #,CCR Dy,SR #,SR y,Ax Ry,Rc list,x y,list #,Dx y,Dx y,Dx x x none Dy,x y,Dx #,Dx none none none Dx # Dy,x y,Dx y,Ax #,Dx #,x Dy,Dx Dn none OPERAND SIZE 8,16,32 16 16 8 16 16,32 32 32 32 32 8 32 16 x 16 32 32 x 32 32 16 x 16 32 32 x 32 32 32 32 none 32 32 32 32 none none none 8 16 32 32 32 32 32 32 16 none OPERATION y x CCR Dx SR Dx Dy CCR # CCR Source SR Source Destination Ry Rc Listed Registers Destination Source Listed Registers Sign-extended Immediate Data Destination Source x Destination Destination Signed operation Source x Destination Destination Unsigned operation 0 - Destination Destination 0 - Destination- X Destination PC + 2 PC; Synchronize Pipelines ~ Destination Destination Source | Destination Destination Immediate Data | Destination Destination SP - 4 SP; Address of (SP) Set PST= $4 (SP+2) SR; SP+4 SP; (SP) PC; SP + FormatField SP (SP) PC; SP + 4 SP If Condition True, Then 1's Destination; Else 0's Destination Immediate Data SR; Enter Stopped State Destination - Source Destination Destination - Source Destination Destination - Immediate Data Destination Destination - Immediate data Destination Destination - Source - X Destination MSW of Dn LSW of Dn SP - 4 SP;PC (SP); SP - 2 SP;SR (SP); SP - 2 SP; Format (SP); Vector Address PC PC + 2 PC PC + 4 PC PC + 6 PC Set Condition Codes Ax SP; (SP) Ax; SP + 4 SP y DDATA port y Debug Module y Ax y yMCF5202 USER'S MANUALMCF5202 series of integrated circuits. A signal block diagram is shown in Figure 2-1 below.MCF5202 /3 AA DTIP DA[1:0] TEA TBI TRANSFER CONTROLMCF5202 Block DiagramMCF5202 USER'S MANUALMCF5202 Signal IndexMCF5202 USER'S MANUALMCF5202 processor is the bus master, it drives the R/W signal to indicate the direction of subsequent data transfers. It is driven high during read bus cycles and driven low during write bus cycles. This signal is three-stated when the MCF5202 device is not the bus master.MCF5202 processor asserts this signal during the first clock cycle when a valid address is driven on A/D[31:0] and is negated in the following clock cycle. TS is three-stated when the MCF5202 device is not the bus master.MCF5202 processor outputs these signals to indicate the requested data transfer size. Table 2-2 shows the definition of the bus request size encodings. When the MCF5202 device is not the bus master, these signals are three-stated.MCF5202 USER'S MANUALMCF5202 processor when it is the bus master indicating the type of access for the current bus access. Table 2-3 shows the encoding definitions.MCF5202 USER'S MANUALMCF5202 device asserts this signal to indicate that the bus cycle data phase is in progress. It is asserted on the rising CLK edge where AA is asserted. DTIP is negated at the completion of the current transfer. DTIP may be negated at any time in the bus cycle to indicate that the transfer has been aborted. When the MCF5202 processor is not the bus master, DTIP is three-stated.MCF5202 USER'S MANUALMCF5202 processor begins an access to the external bus with no other internal accesses pending, and BR remains negated until another internal request occurs.MCF5202 device can control the bus at the next rising edge of CLK. When the arbiter negates BG, the MCF5202 processor must relinquish the bus as soon as the current transfer is complete. The external arbiter must not grant the bus to any other master until both BD and BG are negated.MCF5202 device asserts this output signal to indicate that the MCF5202 is the current master. If the MCF5202 processor loses bus mastership during a bus transfer, it will complete the last transfer of the current access, negate BD, and three-state all bus signals on the rising edge of CLK. DTIP will be driven to a high level and three-stated one clock after the other bus signals. If the MCF5202 device loses bus mastership during an idle clock cycle, it will three-state all bus signals on the rising edge of CLK.MCF5202 USER'S MANUALMCF5202 processor synchronous clock. CLK is used internally to clock or sequence the internal logic of the MCF5202 processor.MCF5202 processor to enter reset exception processing. When RST is recognized, the A/D bus, TT, SIZ, R/W, DTIP, ATM and TS will be threestated. BR and BD will be negated.MCF5202 processor status. The timing is synchronous with the processor clock (CLK) and the status may not be related to the current bus transfer. Table 2-6 shows the encodings of these signals. . Table 2-6. MCF5202 Processor PST DefinitionMCF5202 supports JTAG and contains an internal debug module. Several of the control pins for these modes are multiplexed, so users should be careful when the system requires both modes.MCF5202 USER'S MANUALMCF5202 . Table 2-7 shows the encoding for these signals. For normal operations not using the debug module, tie these signals to a logic low.MCF5202 processor clock. Various TAP operations occur on the rising or falling edge of TCK. The internal TAP controller logic is designed in such a way that holding TCK high or low for an indefinite period of time will not cause the TAP test logic to lose state information. If TCK is not used, it should be tied to ground.MCF5202 processor. Even with this asynchronous signal, Motorola recommends that TRST only make a 0 to 1 (asserted to negated) transition while TMS is held at a logic 1 value. TRST has an internal pullup so that if it is not driven low its value will default to a logic level of 1. However, if TRST will not be used, it can either be tied to ground or, if TCK is clocked, it can be tied to VDD. The former connection will place the TAP controller in the test logic reset state immediately, while the later connection will cause the TAP controller (if TMS is a logic 1) to eventually end up in the test logic reset state after 5 clocks of TCK.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUAL Dx Dx Dx Dx Dx Dx Dx Dx Rn 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) (An) 1(0/1) 1(0/1) 1(0/1) N N N N N N N N 3(1/0) 3(1/0) 2(1/0) (An)+ 1(0/1) 1(0/1) 1(0/1) N N N N N N N N 3(1/0) 3(1/0) 2(1/0) EFFECTIVE ADDRESS -(An) (d16,An) (d8,An,Xn*SF) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 1(0/1) 2(0/1) N N N N N N N N N N N N N N N N N N N N N N N N 3(1/0) 3(1/0) 4(1/0) 3(1/0) 3(1/0) 4(1/0) 2(1/0) 2(1/0) 3(1/0) xxx.wl 1(0/1) 1(0/1) 1(0/1) N N N N N N N N 3(1/0) 3(1/0) 2(1/0) #xxx N N N N N N N N N N N 1(0/0) 1(0/0) 1(0/0)MCF5202 USEROS MANUAL ,Rx Dy, #imm,Dx #imm, Dy,Dx ,Rx Dy, #imm,Dx ,Dx ,Dx Dy, #imm, Dy, #imm, Dy, #imm, Dy, #imm, ,Rx #imm,Dx Dy, #imm,Dx ,Ax ,Dx ,Dx #imm,Dx ,Dx ,Dx ,Dx ,Dx ,Rx Dy, #imm,Dx ,Rx Dy, #imm,Dx #imm, Dy,Dx Rn 1(0/0) N 1(0/0) 1(0/0) 1(0/0) 1(0/0) N 1(0/0) 1(0/0) 1(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 2(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) 1(0/0) N 1(0/0) 1(0/0) N 9(0/0) 9(0/0) 18(0/0) 18(0/0) 1(0/0) N 1(0/0) 1(0/0) N 1(0/0) 1(0/0) 1(0/0) (An) 3(1/0) 3(1/1) N 3(1/1) N 3(1/0) 3(1/1) N N N 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/0) N 3(1/1) N 1(0/0) N N N 11(1/0) 11(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/1) N 3(1/0) 3(1/1) N 3(1/1) N (An)+ 3(1/0) 3(1/1) N 3(1/1) N 3(1/0) 3(1/1) N N N 4(1/1) 4(1/1) 4(1/1) 4(1/1) 41/1) 4(1/1) 3(1/1) 3(1/1) 3(1/0) N 3(1/1) N N N N N 11(1/0) 11(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/1) N 3(1/0) 3(1/1) N 3(1/1) N EFFECTIVE ADDRESS (d16,An) -(An) (d16,PC) 3(1/0) 3(1/0) 3(1/1) 3(1/1) N N 3(1/1) 3(1/1) N N 3(1/0) 3(1/0) 3(1/1) 3(1/1) N N N N N N 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/0) 3(1/0) N N 3(1/1) 3(1/1) N N N 1(0/0) N N N N N N 11(1/0) 11(1/0) 11(1/0) 11(1/0) 20(1/0) 20(1/0) 20(1/0) 20(1/0) 3(1/0) 3(1/0) 3(1/1) 3(1/1) N N 3(1/0) 3(1/0) 3(1/1) 3(1/1) N N 3(1/1) 3(1/1) N N (d8,An,Xn*SF) (d8,PC,Xn*SF) 4(1/0) 4(1/1) N 4(1/1) N 4(1/0) 4(1/1) N N N 5(1/1) N 5(1/1) N 5(1/1) N 4(1/1) N 4(1/0) N 4(1/1) N 2(0/0) N N N 12(1/0) 12(1/0) N N 4(1/0) 4(1/1) N 4(1/0) 4(1/1) N 4(1/1) N xxx.wl 3(1/0) 3(1/1) N 3(1/1) N 3(1/0) 3(1/1) N N N 4(1/1) N 4(1/1) N 4(1/1) N 3(1/1) N 3(1/0) N 3(1/1) N 1(0/0) N N N 11(1/0) 11(1/0) N N 3(1/0) 3(1/1) N 3(1/0) 3(1/1) N 3(1/1) N #xxx 1(0/0) N N N N 1(0/0) N N 1(0/0) 1(0/0) N N N N N N N 1(0/0) 1(0/0) N N N N 1(0/0) 1(0/0) 1(0/0) 9(0/0) 9(0/0) N N 1(0/0) N N 1(0/0) N N N NMCF5202 USEROS MANUAL Ay,#imm CCR,Dx ,CCR SR,Dx ,SR Rn 2(0/1) 1(0/0) 1(0/0) 1(0/0) 7(0/0) 9(0/1) N N 3(0/0) N 1(0/0) #imm N (An) N N N N N N 1+n(n/0) 1+n(0/n) N 2(0/1) N N (An)+ N N N N N N N N N N N N EFFECTIVE ADDRESS -(An) (d16,An) (d8,An,Xn*SF) N N N N N N N N N N N N N N N N N N N N N N 1+n(n/0) 1+n(0/n) N 2(0/1) 3 N N N N N N N 3(0/1) 4 N N xxx.wl N N N N N N N N N 2(0/1) N N N N N N N 3(1/0) N #xxx N N 1(0/0) N 7(0/0) 1 N N N N N N 3(0/0) 2 15(1/2) N N N N 3(1/0) N,&list MOVEM.L &list, NOP PEA PULSE STOP N 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) WDEBUG N 5(2/0) N N 5(2/0) N n is the number of registers moved by the MOVEM opcode. 1If a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0). 2The execution time for STOP is the time required until the processor begins sampling continuously for interrupts. 3 PEA execution times are the same for (d16,PC) 4 PEA execution times are the same for (d8,PC,Xn*SF)MCF5202 USEROS MANUAL Rn N N N N N (An) N 3(0/0) 3(0/1) N N (An)+ N N N 10(2/0) 5(1/0) EFFECTIVE ADDRESS (d16,An) -(An) (d16,PC) N 3(0/1) N 3(0/0) N 3(0/1) N N N N (d8,An,Xi*SF) (d8,PC,Xi*SF) N 4(0/0) 4(0/1) N N xxx.wl N 3(0/0) 3(0/1) N N #xxx N N N N N MCF5202 USEROS MANUALMCF5202 contains a nonblocking, 2-kbyte, 4-way set-associative, unified (instruction and data) cache with a 16-byte line size. The cache improves system performance by providing low latency data to the MCF5202 instruction and data pipes. This decouples processor performance from system memory performance and increases bus availability for alternate bus masters. The MCF5202 nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache allocation) is in progress. As shown in Figure 4-1, both instruction and data accesses are performed using a single bus connected to the cache. All addresses from the processor to the cache are physical addresses. If the address matches one of the cache entries, the access hits in the cache. For a read operation, the cache supplies the data to the processor, and for a write operation, the data from the processor updates the cache. If the access does not match one of the cache entries (misses in the cache) or a write access must be written through to memory, the cache performs a bus cycle on the MBUS and correspondingly on the external bus by way of the system bus controller (SBC). Throughout this chapter, all cache accesses on the MBUS have a corresponding access on the external bus by way of the SBC.MCF5202 Unified CacheMCF5202 USER'S MANUALMCF5202 does not implement a bus snooper. Users must maintain cache coherency with other possible bus masters via software.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUAL 4-7MCF5202 cache. The instruction format is shown below.MCF5202 USER'S MANUALMCF5202 , only cache lines 0, 1, 2, and 3 are valid. The following code example flushes the entire MCF5202 unified cache:MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 provides limited support for maintaining cache coherency in multimaster environments. Both writethrough and copyback memory update techniques are supported to maintain coherency between the cache and memory. The MCF5202 cache does not support snooping (i.e., cache coherency is not supported while alternate masters are using the bus).MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 bus interface supports synchronous, dynamic bus-size and bursted data transfers between the processor and other devices in the system. This section provides a functional description of the bus, the signals that control the bus, and the bus cycles provided for data transfer operations. The waveforms in this document show the bus activity for an MCF5202 processor. Descriptions of bus arbitration and the reset operation are also included.MCF5202 processor uses a single clock signal CLK to generate its internal clocks as well as the bus clock. Therefore, the external bus operates at the same speed as the processor's internal clock rate, where all bus operations are synchronous to the rising edge of CLK. Figure 5-1 illustrates the general relationship between CLK and most input and output signals.MCF5202 processor inputs (other than IPL[2:0], BKPT, and RST signals) must be stable during the sample window defined by tsi and thi (see Figure 51) to guarantee proper operation. The internally synchronized IPL[2:0], BKPT, and RST signals resolve the input to a valid level before being used. The MCF5202 outputs begin to transition on the rising edge of CLK.MCF5202 device will multiplex only addresses and data on A/D[31:16]. A/D[15:0] will drive the current address for the duration of the transfer, incrementing A/D[3:0] on burst accesses. Figure 5-2 displays a simple example of the MCF5202 processor executing a longword write followed by a longword read terminated with a bus error. The assertion of TEA during any portion of the transfer will abort the transfer. All figures display logical waveforms and do not indicate any timing relationships unless noted.MCF5202 device bursts all accesses to a port smaller than the transfer size accesses unless TBI is asserted during the first data acknowledge cycle of the transfer. The level of TBI during the remainder of the access has no affect on the transfer. Figures 5-3 through 5-6 show examples of various types of burst read/write cycles to dynamically sized ports, including burst-inhibited cycles. In these figures, AA is tied low.MCF5202 processor supports both interrupt- and autovector-acknowledge cycles. In either case, if the transfer is terminated with the assertion of TEA, a spurious interrupt exception is taken. Figure 5-7 displays an interrupt-acknowledge cycle. The cycle is similar to a byte read, except the access is in CPU space, TT = 11. The interrupt level being acknowledged is driven onto A/D[4:2], while A/D[31:5] are driven high and A/D[1:0] are driven low. The system drives the interrupt vector onto A/D[31:24], asserting DA, to terminate the access. During the acknowledge cycle, AVEC can be asserted, forcing internal generation of the vector number. If AVEC is asserted, vector data is not required to be driven. The IPL signals should remain valid until the acknowledge cycle is complete.MCF5202 processor supports multimaster system designs by requesting the bus fromMCF5202 device to another master. The external arbiter may offer the bus to another master any time both BD and BG are negated. The MCF5202 monitors its bus grant (BG) signal to determine when it should become bus master and will start to drive the bus at the rising edge of the clock in which BG is recognized asserted. Figure 5-8 shows two scenarios of BG being negated. In the first, the MCF5202 is bus master and the bus is idle. On the rising CLK edge where BG is recognized negated, the MCF5202 device will drive the bus to a high-impedance level. In the second case, BG is negated within a bus cycle. The MCF5202 processor will complete the bus access by driving BD negated and driving all bus signals to a high-impedance level. If DTIP is tied to another master, there may be some period of time when this signal may be driven high by 2 separate drivers with both pins driving high before the previous master places its pin in a three-state mode.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 processors include dedicated user-accessible test logic that is fully compliant with the IEEE standard 1149.1 -1993 Standard test access port and boundary- scan architecture. The following description should be used in conjunction with the supporting IEEE document listed above. This section includes the description of those chip-specific items that the IEEE standard requires as well as those items specific to the MCF5202 implementation. The MCF5202 JTAG test architecture implementation currently supports circuit board test strategies that are based on the IEEE standard. This architecture provides access to all of the data and chip control pins from the board edge connector through the standard four-pin test access port (TAP) and the active-low JTAG reset pin, TRST. The test logic itself uses a static design and is wholly independent of the system logic, except where the JTAG is subordinate to other complimentary test modes (used for manufacturing test support). When in subordinate mode, the JTAG test logic is placed in reset and the TAP pins can be used for other purposes in accordance with the rules and restrictions set forth using a JTAG compliance-enable pin. The MCF5202 JTAG implementation can * Perform boundary-scan operations to test circuit board electrical continuity * Bypass the MCF5202 device by reducing the Shift Register path to a single cell * Sample the MCF5202 system pins during operation and transparently shift out the result * Set the MCF5202 output drive pins to fixed logic values while reducing the Shift Register path to a single cell * Protect the MCF5202 system output and input pins from backdriving and random toggling (such as during in-circuit testing) by placing all system signal pins to high impedanceMCF5202 USER'S MANUALMCF5202 implementation of the 1149.1 IEEE Standard. The test logic includes several Test Data Registers, an Instruction Register, instruction register control decode, and a 16-state dedicated TAP controller (defined in Figure 7-3).MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 IEEE 1149.1 implementation uses a 3-bit Instruction Shift Register without parity. This register transfers its value to a parallel hold register and applies one of eight possible instructions on the falling edge of TCK when the TAP state machine is in the update-IR state. The instructions can be loaded into the shift portion of the register by placing the serial data on the TDI pin prior to each rising edge of TCK. The MSB of the Instruction Shift Register is the bit closest to the TDI pin and the LSB is the bit closest to the TDO pin.MCF5202 USER'S MANUALMCF5202 implementation and are described in the 1149.1. 7.3.1.1 EXTEST INSTRUCTION. The external test instruction (EXTEST) selects the Boundary Scan Register. The EXTEST instruction forces all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded (with the SAMPLE/ PRELOAD instruction) and held in the Boundary Scan Update Registers. The EXTEST instruction can also configure the direction of bidirectional pins and establish highimpedance states on some pins. The EXTEST instruction becomes active on the falling edge of TCK in the update-IR state when the data held in the Instruction Shift Register is equivalent to octal 0. 7.3.1.2 SAMPLE/PRELOAD INSTRUCTION. The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a way to obtain a sample of the system data and control signals present at the MCF5202 input pins and just prior to the boundary scan cell at the output pins. This sampling occurs on the rising edge of TCK in the captureDR state when an instruction encoding of octal 4 is resident in the instruction register. Users can observe this sampled data by shifting it through the Boundary Scan Register to the output TDO by using the shift-DR state. Both the data capture and the shift operation are transparent to system operation. Users are responsible for providing some form of external synchronization to achieve meaningful results because there is no internal synchronization between TCK and the system clock, CLK. The second function of the SAMPLE/PRELOAD instruction is to initialize the Boundary Scan Register update cells before selecting EXTEST or CLAMP. This is achieved by ignoring the data being shifted out of the TDO pin while shifting in initialization data. The update-DR state in conjunction with the falling edge of TCK can then transfer this data to the update cells. This data will be applied to the external output pins when one of the instructions listed above is applied.MCF5202 USER'S MANUALMCF5202 processor becomes the device under test on a board design with multiple chips on the overall 1149.1 defined boundary scan chain. The Bypass Register has been implemented in accordance with 1149.1 so that the Shift Register stage is set to logic zero on the rising edge of TCK following entry into the captureDR state. Therefore, the first bit to be shifted out after selecting the Bypass Register is always a logic zero (this is to differentiate a part that supports an IDCODE register from a part that supports only the Bypass Register). The BYPASS instruction becomes active on the falling edge of TCK in the update-IR state when the data held in the Instruction Shift Register is equivalent to a octal 7.MCF5202 model. This Boundary Scan Register can be connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. This register captures signal pin data on the input pins, forces fixed values on the output signal pins, and selects the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins.MCF5202 USER'S MANUALMCF5202 includes an IEEE 1149.1-compliant Bypass Register, which creates a single bit shift register path from TDI to the Bypass Register to TDO when the BYPASS instruction is selected.MCF5202 USER'S MANUALMCF5202 , visit the following Internet address: http://pirs.aus.sps.mot.com/aesop/aesop.htmlMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 contains hardware support for data misalignment and therefore this is not an issue for family members. On a ROM monitor, it is often necessary to provide a means by which a user program is executed given a certain starting address. This is often implemented by placing an exception stack frame and then performing an RTE. If this is the case, the header files that define what a stack frame looks like would require modification to reflect the ColdFire stack frame format.MCF5202 USER'S MANUALMCF5202 USER'S MANUALMCF5202 processor.MCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 USEROS MANUALMCF5202 Power Consumption 16MHZ 25MHz 33MHz 302 448 589 UNITS mWMCF5202 USEROS MANUALMCF5202 USER'S MANUALMCF5202 MCF5202 PinoutMCF5202 USER'S MANUAL
